1. Field of the Invention
The present invention relates to a clock supply bias circuit for a prescaler (frequency dividing circuit) driven by a single-phase clock, and more particularly, to a clock supply bias circuit for a prescaler having a CMOS structure.
2. Description of the Prior Art
In recent years, in RF front-end ICs for mobile communication and broadband communication, there are increasing needs for system IC and cost reduction.
Conventionally, the BiCMOS process capable of integrating a bipolar transistor having an excellent high-frequency characteristic and a CMOS appropriate to high-integration digital circuit into 1 chip has been used in forming an LSI RF front end. In accordance with recent development of finer and high frequency CMOS, an RF unit using CMOS has been developed.
The CMOS RF unit is advantageous in that a complete 1-chip system IC in which CMOS constitutes a baseband unit as well as an RF unit can be realized, and that the IC can be manufactured through a reduced number of process steps in comparison with the BiCMOS process.
The RF front end requires a frequency synthesizer for channel selection. The frequency synthesizer is constructed employing a prescaler, a counter, a phase comparator, a charge pump and the like therein. Especially, the prescaler to which an RF signal is inputted requires a high frequency characteristic.
Conventionally, to realize the high-frequency prescaler, the BiCMOS process has been mainly employed, and an LSI prescaler operating at frequencies up to 3 GHz has been realized.
Furthermore, to realize a high-speed prescaler employing CMOS, the Extended True-Single-Phase-Clock (E-TSPC) technique has been proposed as a technique for achieving high speed, high integration and low electric consumption. However, the maximum operation frequency to be achieved by this technique is about 3 GHz.
FIG. 1 shows the construction of a ⅘frequency dividing prescaler using the E-TSPC technique.
As shown in FIG. 1, in the ⅘frequency dividing prescaler, a single-phase clock signal is inputted from a clock terminal CLK indicated by a bold line, through a clock input line, into nMOS transistors N51, N53 and a pMOS transistor P53 of DFF1, an nMOS transistor N71 and a pMOS transistor P72 of DFF2, nMOS transistors N91, N93 and a pMOS transistor P93 of DFF3, a pMOS transistor P54 of a NOR circuit, an nMOS transistor N59 and pMOS transistor P57 of a BUFF (buffer) circuit. In this case, to make the nMOS and pMOS transistors have their maximum drive capability, generally a clock voltage of the single-phase clock signal is set at a value between a positive power-supply voltage VDD and a negative power-supply voltage VSS, as shown in the figure.
However, in the case where the clock voltage consisting of the single-phase clock signal is used and an input signal frequency is divided by 2 in the prescaler, a frequency dividing characteristic of the DFF circuit presents dependency on input signal frequency as shown in FIG. 9.
As shown in FIG. 9, when the input signal frequency is 3.813 GHz or higher, the signal frequency cannot be divided.
In consideration of the recent trend that 5 GHz band frequencies typified such as by IEEE 802.11a to communicate using radio frequency has gradually been available and therefore, an ultra-fast prescaler has strongly been required to operate at high frequencies up to 5 GHz using CMOS, the frequency characteristic of full-CMOS prescaler has to be further improved.
Accordingly, there arises a problem that the conventional full-CMOS prescaler using the clock voltage of the conventional single-phase clock signal operates in response to the input signal frequency only up to 3.813 GHz and therefore, cannot address the needs for the operation thereof in higher input signal frequencies in the future.
The present invention has its object to provide a clock supply bias circuit, in which an input signal frequency of a single-phase clock drive frequency dividing circuit can be increased in use of a clock voltage of single-phase clock signal, and a single-phase clock drive frequency dividing circuit using the clock supply bias circuit.
The clock supply bias circuit constructed in accordance with the present invention comprises an clock input terminal for receiving a single-phase clock as an input signal and clock output terminals for outputting the input signal as a first clock and a second clock, in which the first clock and the second clock are constructed such that the first clock and the second clock have the same phase as that of the single-phase clock and have different voltages, respectively.
In more detail, the clock supply bias circuit of the present invention is further constructed as follows. That is, the clock supply bias circuit is further constructed such that a first capacitor is connected in series to a positive power supply via a first current control element and disposed between the clock input terminal and a positive power supply, a second capacitor is connected in series to a negative power supply via a second current control element and disposed between the clock input terminal and the negative power supply, a first resistor is connected in parallel with the first capacitor, a second resistor is connected in parallel with the second capacitor, a diode is connected in parallel with the first capacitor and the second capacitor being connected in series, an anode of the diode serves as an output terminal to output the first clock, and a cathode of the diode serves as an output terminal to output the second clock.
In the conventional frequency dividing circuit, the single-phase clock is supplied to gates of nMOS and pMOS transistors of DFF circuit. On the other hand, in a case where the above-described clock supply bias circuit of the present invention is used in the frequency dividing circuit, the clock bias circuit supplies a clock signal in such a manner that a voltage applied to the gate of nMOS transistor of DFF circuit with respect to the p well thereof and a voltage applied to the gate of pMOS transistor of the DFF circuit with respect to the n well thereof are both made larger than that could be achieved using the single-phase clock in the conventional frequency dividing circuit. As a result, the transistors can operate showing gm thereof greatly improved in comparison with that could be achieved in the conventional frequency dividing circuit.
The frequency dividing circuit driven by single-phase clock constructed in accordance with the present invention using the above-described clock supply bias circuit, comprises: a first DFF circuit, a second DFF circuit and a third DFF circuit each consisting of a MOS transistor, a NOR circuit, a NAND circuit, an output buffer circuit and a clock supply bias-circuit, all of the circuits being connected in parallel with each other between a positive power supply and a negative power supply, and the first DFF circuit, the second DFF circuit and the third DFF circuit further being constructed such that all of the DFF circuits are driven by clocks supplied by the clock supply bias circuit, in which
the clock supply bias circuit further comprises:
a clock input terminal;
a first capacitor connected in series to the positive power supply via a first current control element and disposed between the clock input terminal and the positive power supply;
a second capacitor connected in series to the negative power supply via a second current control element and disposed between the clock input terminal and the negative power supply;
a first resistor connected in parallel with the first capacitor;
a second resistor connected in parallel with the second capacitor; and a diode connected in parallel with the first capacitor and the second capacitor being connected in series, the clock supply bias circuit further being constructed such that an anode of the diode serves as a first clock output line and a cathode of the diode serves as a second clock output line,
the first DFF circuit, the second DFF circuit and the third DFF circuit are further constructed such that all of the DFF circuits consist of the same circuit configuration and each of the DFF circuits further comprises:
a first pMOS transistor having a source connected to the positive power supply, a drain connected to a drain of a first nMOS transistor and a gate of a second pMOS transistor, and a gate connected to a data input signal line and a gate of a second nMOS transistor;
the first nMOS transistor having a source connected to a drain of the second nMOS transistor, and a gate connected to a gate of a third nMOS transistor and the first clock output line;
the second pMOS transistor having a source connected to the positive power supply, and a drain connected to a drain of the third nMOS transistor and a gate of a fourth nMOS transistor;
the second nMOS transistor having a source connected to the negative power supply;
the third pMOS transistor having a source connected to the positive power supply, a drain connected to a drain of the fourth nMOS transistor and an output signal line, and a gate connected to the second clock output line;
the third nMOS transistor having a source connected to the negative power supply; and
the fourth nMOS transistor having a source connected to the negative power supply,
the NOR circuit comprises:
a fourth pMOS transistor having a source connected to the positive power supply, a drain connected to a drain of a fifth nMOS transistor, a drain of a sixth nMOS transistor and the data input signal line of the first DFF circuit, and a gate connected to a gate of the sixth nMOS transistor and the output signal line of the third DFF circuit;
the fifth nMOS transistor having a gate connected to a signal input terminal, and a source connected to the negative power supply; and
the sixth nMOS transistor having a source connected to the negative power supply,
the NAND circuit comprises:
a fifth pMOS transistor having a source connected to the positive power supply, a drain connected to a drain of a seventh nMOS transistor and the data input signal line of the second DFF circuit, and a gate connected to a gate of the seventh nMOS transistor and the output signal line of the third DFF circuit;
the seventh nMOS transistor having a source connected to a drain of an eighth nMOS transistor; and
the eighth nMOS transistor having a source connected to the negative power supply, and a gate connected to the output signal line of the first DFF circuit,
the output buffer circuit comprises:
a sixth pMOS transistor having a source connected to the positive power supply, a drain connected to a drain of a ninth nMOS transistor, a gate of a seventh pMOS transistor, a gate of a tenth nMOS transistor and the second output signal terminal, and a gate connected to a gate of the ninth nMOS transistor, the output signal line of the second DFF circuit and the data input signal line of the third DFF circuit;
the ninth nMOS transistor having a source connected to the negative power supply;
the seventh pMOS transistor having a drain connected to a drain of the tenth nMOS transistor and the first output signal terminal; and
the tenth nMOS transistor having a source connected to the negative power supply.
As described above, the frequency dividing circuit driven by single-phase clock through the clock supply bias circuit constructed in accordance with the present invention has the following advantages. That is, first, the single-phase clock inputted to the clock supply bias circuit is divided into the associated clock signals to drive nMOS and pMOS transistors, and the resulting clock signals are inputted to the frequency dividing circuit. Thereafter, the resulting clock signals thus created for the nMOS and pMOS transistors by dividing the single-phase clock signal make respective gm of the nMOS and pMOS transistors larger than that could be achieved using the conventional single-phase clock. Accordingly, the frequency dividing performance can be extensively improved in comparison to that observed in the conventional technology.